THU HAS Lab
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Wenjie Xiong
Latest
Survey of Approaches and Techniques for Security Verification of Computer Systems
Leaky Frontends: Micro-Op Cache and Processor Frontend Vulnerabilities
Evaluation of Cache Attacks on Arm Processors and Secure Caches
Understanding Insecurity of Processor Caches Due to Cache Timing-Based Vulnerabilities
A Benchmark Suite for Evaluating Caches’ Vulnerability to Timing Attacks
Analysis of Secure Caches using a Three-Step Model for Timing-Based Attacks
Secure TLBs
Cache timing side-channel vulnerability checking with computation tree logic
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