Jakub Szefer

Latest

• Survey of Approaches and Techniques for Security Verification of Computer Systems
• Securing Reset Operations in NISQ Quantum Computers
• Leaky Frontends: Micro-Op Cache and Processor Frontend Vulnerabilities
• Device- and Locality-Specific Fingerprinting of Shared NISQ Quantum Computers
• New Predictor-Based Attacks in Processors
• Evaluation of Cache Attacks on Arm Processors and Secure Caches
• Understanding Insecurity of Processor Caches Due to Cache Timing-Based Vulnerabilities
• A Benchmark Suite for Evaluating Caches’ Vulnerability to Timing Attacks
• Analysis of Secure Caches using a Three-Step Model for Timing-Based Attacks
• XMSS and Embedded Systems - XMSS Hardware Accelerators for RISC-V
• Secure TLBs
• Cache timing side-channel vulnerability checking with computation tree logic